Analog-to-digital converters (ADCs) convert time-discrete analog input values to a digital form. A type of ADC, the successive approximation (SA) ADC, digitizes the analog input values using a successive approximation search algorithm. While the internal circuitry of the SA-ADC may run at a higher frequency (such as several megahertz (MHz), for example), the sample rate of the SA-ADC is generally a fraction of that frequency (such as several kilohertz (kHz), for example) due to the successive approximation search algorithm used. For example, normally each bit of the SA-ADC is fully realized prior to proceeding on to the next bit.
In general, each bit-weight of a successive approximation register (SAR) arrangement of a SA-ADC may be represented by a physical element (e.g., capacitor, resistor, current source, etc.). A search algorithm may be used with the physical elements to determine the closest digital approximation to an analog input value. Commonly, a binary search algorithm is used with an arrangement having physical elements with binary bit-weights, for example. While this technique may be the simplest to implement, it is generally not the most power efficient or the fastest. Split-capacitor techniques can be more power efficient, but have a higher complexity. A typical non-binary or “redundant” technique can be faster, but has an even higher complexity since it normally uses a non-binary search algorithm. Also, some non-binary techniques can be difficult to calibrate.